Periodic digital signals are commonly used in a variety of electronic devices, such as memory devices. Probably the most common of periodic digital signals are clocks that are typically used to establish the timing of a digital signal or the timing at which an operation is performed on a digital signal. For example, data signals are typically coupled to and from memory devices in synchronism with a clock or data strobe.
Clock circuits included in the electronic device provide internal clocks that are used for timing various operations. The internal clocks may be based on external clocks provided to the electronic device. An example clock circuit may include a delay-locked loop (DLL). A typical DLL uses a delay line including a large number of delay stages. A reference clock is applied to the delay line, and it propagates through the delay line to the final delay stage, which outputs a delayed clock. The phase of the delayed clock is compared to the phase of the reference clock to generate a phase error signal. The phase error signal is used to adjust the delay provided by the delay stages in the delay line until the phase of the delayed clock is locked to the phase of the reference clock. The DLL is considered to have obtained a locked condition when this occurs. The delayed clock may then be provided to other circuits of the electronic device for timing operations.
As the operating speed of electronic devices increases, the frequencies of clock signals needed to operate the electronic devices at these higher speeds also increase. One difficulty encountered with these higher clock speeds is the difficulty for circuits of a DLL to determine a phase relationship between the delayed clock and reference clock for adjusting delay.
An approach that has been used to alleviate this problem is to divide a higher frequency clock to generate lower frequency clocks having clock transitions that coincide with clock transitions of the higher frequency clock. Typical clock divider circuits included in DLLs, however, provide divided clocks having unpredictable phase relationships with the higher frequency clock, which may result in longer than desirable time for the DLL to reach a locked condition. Therefore, it may be desirable to have alternative designs for clock divider circuits and DLLs.